1 Models for VLSI Manufacturing Yield. - Fault-Free or Fault-Tolerant VLSI Manufacturing. - Yield Models Comparative Study. - 2 Models for Defects and Yield. - A Unified Approach to Yield Analysis of Defect Tolerant Circuits. - Systematic Extraction of Critical Areas From IC Layouts. - The Effect on Yield of Clustering and Radial Variations in Defect Density. - 3 Implementation of Wafer Scale Integration. - Practical Experiences in the Design of a Wafer Scale 2-D Array. - Yield Evaluation of a Soft-Configurable WSI Switch Network. - ASP Modules: WSI Building-Blocks for Cost-Effective Parallel Computing. - 4 Fault Tolerance. - Fault-Tolerant k-out-of-n Logic Unit Network With Minimum Interconnection. - Extended Duplex Fault Tolerant System With Integrated Control Flow Checking. - Experience in Functional Test and Fault Coverage in a Silicon Compiler. - 5 Array Processors. - APES: An Evaluation Environment of Fault-Tolerance Capabilities of Array Processors. - Comparison of Reconfiguration Schemes for Defect Tolerant Mesh Arrays. - An Integer Linear Programming Approach to General Fault Covering Problems. - Probabilistic Analysis of Memory Repair and Reconfiguration Heuristics. - Arithmetic-Based Diagnostics in VLSI Array Processors. - 6 New Approaches and Issues. - Yield Improvement Through X-RAY Lithography. - Reliability Analysis of Application-Specific Architectures. - Fault Tolerance in Analog VLSI: Case Study of a Focal Plane Processor. - 7 Yield and Manufacturing Defects. - Yield Model With Critical Geometry Analysis for Yield Projection from Test Sites on a Wafer Basis With Confidence Limits. - SRAM/TEG Yield Methodology. - A Fault Detection and Tolerance Tradeoff Evaluation Methodology for VLSI Systems. - 8 Designs for Wafer Scale Integration. - A Hypercube Design on WSI. - An EfficientReconfiguration Scheme for WSI of Cube-Connected Cycles With Bounded Channel Width. - A Communication Scheme for Defect Tolerant Arrays. Language: English